In order to perform debugging, many devices (e.g., computing systems) include a set of counters that track the number of times an event occurs (e.g., writes to RAM). Typically, the outputs of the counters are available via an interface, such as a CPU interface, that allows the values in the counters to be read like registers. Such an arrangement has several drawbacks. For example, the CPU generally must stop its operation to read the registers. Stopping the CPU alters the system behavior. It may also take many clocks for the CPU to read each register. This makes it difficult to use the counters to observe fine grained behavior such as pipeline stalls and to see how two behaviors are correlated.